bondtechボンドテックについてテクノロジーマーケットプロダクト
Facing the big up-and-down of the semiconductor market, MEMS market has been steadily growing. Because MEMS device has characteristic elements with moving parts, protective packages for them are of increasing importance. These packages are easily being high cost of production comparing to the semiconductor packages. In this reason, main challenge is how to keep these costs lower. We assume that Wafer Level Package (WLP) would become main stream in MEMS package. Encapsulation in wafer level makes reduction of test process and drastic downsizing. Besides, "Wafer bonding technology" as one of WLP package technology in wafer level is also starting to attract attention because of the similar architecture to WLP which has hollow structure of image sensor.
THREE-DIMENSIONAL LSI
bondtech_img LSI has achieved high performance and low power consumption by micro-fabrication technology. Nowadays because of the current issues such as increasing leak current caused by the minimization of the physical size, technical limitation of wavelengths in photolithography process, etc., another technology by three-dimensional lamination that helps to enhance the LSI performance has come to the front. Its trigger is the electrode infrastructure connecting chips with via (hole) penetrating Si chip. Comparing to the conventional two-dimensional IC, three-dimensional lamination connects chips by shortest path, making shorten the IC path and is of advantage to the enhanced performance like size reduction, faster connection and low power consumption. Furthermore, compared to the lamination between chips or lamination between packages, there are great hopes towards the lamination at the wafer level that it achieves higher productivity and higher performance.
CMOS MOUNTING
Semiconductor companies evolve to become a successor to hand-made or machining process for assembling and manufacturing mobile phone camera modules. Thanks to MEMS processing technology, we are stepping into commercial phase of using resin lens of which heat resistance over 250°C. By low cost and high heat resistant lens, electrode (TSV) and wafer level implementation, we forecast "wafer level camera module" that would practice all camera module processes including image sensor and lens in future. From its realization, we are able to manufacture with relatively low cost comparing to existing resin lens. There are great hopes that this CMOS image sensor would be utilized not only for mobile phone but also note PC and handy game console. Besides, CMOS image sensor has received much attention in automotive industry.

OPTICAL INTECONNECTION BOARD、OPTICAL MODULE

In the field of optical communication, in Si bench unit for connecting the optical fiber, the light receiving element and LD (laser diode), the passive alignment method for chip mounting with high precision in sub-micron has been demanded. In conventional Au / Sn solder the displacement during melting has been a hinder. However, it is possible to bond in the solid phase at a low temperature and room temperature ~ 150℃ in the atmosphere by processing the surface activation by Ar plasma. The bonding accuracy dramatically improves and the productivity also does because the bonding without melting can be done in the second. Also, more reliable implementation by adopting as an electrode of Au other than the solder is performed. It is a field that implementation progresses more in passive alignment multi-channel by Vicsel.
マーケットMEMS WAFER LEVEL PACKAGE (WLP)THREE-DIMENSIONAL LSICMOS MOUNTINGOPTICAL INTECONNECTION BOARD、OPTICAL MODULE